This invention relates to a semiconductor device and fabrication thereof and, more particularly, to the fabrication of a silicon layer having increased surface area for use in a semiconductor device.
Semiconductor devices, including Dynamic Random Access Memory devices (DRAMs), utilize storage capacitors to retain data. In the manufacture of DRAMs a polysilicon layer is typically used as the bottom electrode (storage plate electrode) of the cell capacitor. With the density of storage cells packed into today""s DRAM devices, a storage plate electrode may require a large surface area to provide sufficient capacitance for data storage and retrieval. In order to gain surface area for the storage plate electrode the polysilicon layer may be deposited using conditions to produce a very rough film, i.e. one with a large surface area.
As evidenced by an article in Applied Physics Letters, Volume 79, Number 3, 16 July 2001, by Ostraat et al., titled: xe2x80x9cSynthesis and characterization of aerosol silicon nanocrystal nonvolatile floating-gate memory devicesxe2x80x9d and by an article in Journal of The Electrochemical Society, by Ostraat et al., 148 (5) G265-G270 (2001), titled: xe2x80x9cUltraclean Two-Stage Aerosol Reactor for Production of Oxide-Passivated Silicon Nanoparticles for Novel Memory Devices,xe2x80x9d an aerosol delivery method has been developed to form silicon nanocrystals. The disclosure of each of the forgoing publications is incorporated by reference.
A significant focus-of the present invention comprises techniques to form a silicon nanocrystal layer having a significantly enhanced surface area for use in semiconductor devices, such as DRAMs, which will become apparent to those skilled in the art from the following disclosure.
A first exemplary implementation of the present invention includes a storage capacitor for a semiconductor assembly comprising a substantially continuous porous conductive storage plate comprising silicon nanocrystals residing along a surface of a planarized conductive material and along a surface of a planarized insulative material adjacent the conductive material, a capacitor cell dielectric and an overlying conductive top plate.
The capacitor is formed by a semiconductor fabrication method comprising forming silicon nanocrystals on a surface of a conductive material and on a surface of an insulative material adjacent the conductive material, the silicon nanocrystals contain conductive impurities and are adjoined to formed a substantially continuous porous conductive layer. Next, a cell dielectric layer is formed over the silicon nanocrystals and finally, a conductive top capacitor electrode is formed over the cell dielectric layer.
A second exemplary implementation of the present invention includes a planar storage capacitor for a semiconductor assembly that is formed following the procedures of the first exemplary implementation. The second exemplary implementation demonstrates the versatile nature of the present invention.